Perr generation что это в биосе
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Perr generation что это в биосе

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The list of UEFI feature(Workload Optimized 2)¶

UEFI settings of Workload optimized 2 is as follows. In addition, customers can not change the following settings.

Boot Feature¶

Setting items (key)

Value set as (Default)

Instead of the startup the logo display screen, it is set to display the POST screen.

In order to support an OS other than UEFI-compatible OS, it is the corresponding set to the traditional BIOS using the CSM.

Set the display mode of the option ROM. Force BIOS is selected to use the Option ROM display mode that has been set by the system BIOS.

Set the power-up state of the NUMLOCK key.

If an error occurs, and then force the system to select [Enable] to wait until the key <F1> is pressed.

In the setting to perform the notification of the interrupt signal, it is set to take effect if the option ROM is installed on more than one expansion card.

After a failed initial boot, it is set to be able to re-boot the system from the boot device.

This setting is to enable the watchdog timer to restart the system.

The system will control how to shut down when the power button is pressed.

This setting is for the power state at the time of recovery after a power failure. Currently it is set to be able to resume the last of the power state before power loss.

CPU Configuration¶

Setting items (key)

Value set as (Default)

It is the monitoring settings of BIOS to reduce the level of electromagnetic interference.

It is the support setting for the Intel Hyper-Threading technology to improve the performance of the CPU.

Valid setting of the CPU core. In the default setting, it is set “0” in order to enable all of the CPU cores in the system.

It is the setting for the processor that can specify the area and non-area capable of running the application code in memory.

Setting the inventory number (PPIN) control of the protected processor in the system.

It is a setting for read-ahead data and instructions flow from the main memory to the L2 cache and to improve the performance of the CPU.

This setting is for prefetching 128 bytes of cache line as the CPU configuration.

It is a prefetcher setting of the DCU streamer. It prefetches the data stream from the cache memory for the access data and processing the DCU(Data Cache Unit) to speed in order to improve the performance of the CPU.

In order to improve the performance of the network connection and the system, it is a setting for IP prefetcher in the DCU (data cache unit) to prefetch the IP address.

In order to improve the efficiency of the transfer and data access, it is a setting for the Intel DCA (direct cache access) technology.

Based on Intel‘s hyper — threading architecture, each logical processor (thread) is assigned an ID (sensor assistance) of 256 APIC with an 8 — bit bandwidth. The APIC ID extends from 8 bits to 16 bits to provide 512 sensor assistance for each thread to improve CPU performance.

Based on the Intel VT-d, to enable or disable the X2APIC_OPT_OUT Flag on the system.

It is a setting to ensure the security of data utilizing Intel’s AES (Advanced Encryption Standard).

It is a setting in order to use support of Intel Virtualization Technology for support of direct I/O VT-d by reporting I/O device assignment (virtual machine monitor) to VMM via DMAR ACPI table.

Setting items (key)

Value set as (Default)

It is a setting to support the power-saving mode. Customize the power settings of the system is selected as a default setting.

Configure the settings of the power performance bias adjustment by the BIOS or OS.

It s a setting for the control method or how actively is used the particular hardware-based power management options.

Configure the settings of the power-management features.

Setting items (key)

Value set as (Default)

It is a setting that enables a system to adjust the voltage and core frequency of the processor to take advantage of EIST (Enhanced Intel SpeedStep Technology) and automatically reduce power consumption and heat dissipation.

The setting is used in turbo mode in order to enhance the system performance.

This function is to change the P-state Coordination (power-performance state) adjustment type. P — state Coordination is known as SpeedStep for Intel processors. “HW_ALL” to change the P-state Coordination type of the hardware component is selected.

Setting items (key)

Value set as (Default)

This setting is to limit the C-state package registration.

It is a setting for the BIOS to enable the report of the CPU C3 state (ACPI C2) to the OS.

It is a setting for the BIOS to enable the report of the CPU C6 state (ACPI C3) to the OS.

Setting items (key)

Value set as (Default)

it is a setting to carry out the reduction of CPU power consumption, in order to reduce the clock cycle and voltage of the CPU when it’s in a significantly stopped state.

Chipset Configuration¶

Setting items (key)

Value set as (Default)

It is a setting to always be cleared during the electrical tuning EV_DFX Lock bits that are disposed on the processor.

This item is only displayed.

Setting items (key)

Value set as (Default)

It is a setting to support the Intel I/OAT (I/O Acceleration Technology).

It is a setting that does not support the snoop mode for each CB equipment.

It is possible to violate the strict ordering rules on the PCI bus for transactions when a particular transaction is completed before other transactions that have already been enqueued. It is a setting to enable support for Relaxed Ordering.

Setting items (key)

Value set as (Default)

It is an Intel virtualization technology setting. It performs Direct I/O VT-d support by reporting I/O device assignment to VMM (virtual machine monitor) via DMAR ACPI table.

It is a setting to enable the access control service.

It is a setting to enable the interrupt remapping in order to improve the performance of the system.

Setting items (key)

Value set as (Default)

It is a setting to choose the frequency for the QPI link connection.

It is a setting to support the Link L0p in order to reduce the power consumption.

It is a setting to support the Link L1 in order to reduce the power consumption.

It is a setting to enable the Cluster-On-Die support, in order to improve the system performance in cloud computing,

It is a setting is to enable the Early Snoop in order to improve the system performance.

Run the Directory mode, to enable the in memory snoop directory.

It is a setting to enable the Isochronous support in order to meet the QoS requirements (Quality of Service).

Setting items (key)

Value set as (Default)

It is a setting for applying the POR restrictions on the DDR4 frequency and voltage programming.

It is a setting for the maximum memory frequency of on-board memory module.

It is a setting to enhance the integrity of the system performance and data.

It is a setting to set the base line of the power limit at the time of execution of the DRAM module.

it is a setting to set via the automatic voltage control during an idle state of the CPU, thereby reducing power consumption, in order to improve the reliability of PU.

The 4G address space or more memory that is divided between the 2 sockets is set to be enabled.

It is a setting to support the A7 (addressing) mode in order to improve the memory performance.

Setting items (key)

Value set as (Default)

It is a setting to enable the RAS support.

It is a setting to enable support for memory sparing for rank, in order to improve the memory performance.

It is a setting that allows to enable / disable the rank sparing mode.

Patrol scrub is the process that allows the CPU to correct the correctable memory error detected in the memory module and send the correction to the requester (the original source). If this item is enabled, the IO hub is read and if there is no delay due to internal processing, write back 16 K cycles per cache line. With this method, approximately 64 gigabytes of memory behind the IO hub is scrubbed daily.

In this feature, it sets the waiting time of the system before the next patrol scrub is executed.

Demand scrub is a process that enables the CPU to correct correctable memory errors detected in memory modules. If the CPU or I/O issues a demand read command and it is found that the data read from the memory have a correctable error, it corrects the error and sends it to the requester (original source). The memory is updated as well.

It is a setting to support a device tagging.

Setting items (key)

Value set as (Default)

It is a setting to support the legacy USB devices on board.

It is a work-around solution setting for the OS that does not support the XHCI handoff.

It is for operating systems that do not support EHCI handoff. If this item is enabled, EHCI ownership change will be requested by the EHCI driver. Settings are enabled and disabled.

Provides full legacy USB keyboard support for operating systems that do not support legacy USB devices. This setting enables I / O port 60h / 64h emulation support.

It is a setting to enable the USB 3.0 support.

It is a setting to enable the EHCI (Enhanced Host Controller Interface) support of the USB 2.0 connector.

It is a setting to enable the EHCI (Enhanced Host Controller Interface) support of the USB 2.0 connector.

Perr generation что это в биосе

Добрый день моноблок марки HP. Есть такая настройка
PCI SERR## Generation
PCI SERR# Pulette Snooping

Можно включить и отключить.

Только не понятно для чего это.

PCI SERR## Generation
За чем генерировать серийный номер PCI.

Добавлено через 33 секунды
Руководства нету.

Добавлено через 1 минуту
Название опции:
Palette Snooping
Возможные значения:

Enabled, Disabled
Описание:

Данная опция дает возможность синхронизировать цвета видеокарты и изображения, захватываемого с помощью карты ввода-вывода видео (карты видеомонтажа). Если при захвате видео цвета отображаются некорректно, включите эту опцию (Enabled). Во всех остальных случаях опция должна быть выключена (Disabled).

PERR# Generation

Параметр, включающий/отключающий генерирование PERR# (PCI bus parity error) — сигнал ошибки в четности данных, передаваемых по шине PCI. Сигнал PERR# направляется на контролер немаскируемых прерываний (NMI).

PERR# является устойчивым сигналом трех состояний, используемым для сигнализации об обнаружении ошибки четности, связанной с фазой данных. Во время каждой фазы данных транзакции чтения целевой объект передает данные на шину AD. Таким образом, цель состоит в том, чтобы обеспечить правильную четность для инициатора по сигналу PAR, начинающемуся через один такт после подтверждения TRDY# (Target Ready). По завершении каждой фазы данных инициатор обязан зафиксировать содержимое AD (31: 0] и C/BE # [3: 0] и рассчитать ожидаемый паритет в течение тактового цикла, сразу после завершения фазы данных. Затем инициатор фиксирует бит четности, предоставленный целью, из сигнала PAR на следующем переднем фронте тактовых импульсов и сравнивает вычисленную и фактическую четность. Если происходит несовпадение, инициатор затем устанавливает PERR# в течение следующих тактовых импульсов (если это можно сделать с помощью единицы в бите ответа об ошибке четности в его регистре команд.) Утверждение PERR # откладывает завершение каждой фазы данных на два тактовых цикла PCI.

Иными словами, включение данной функции позволяет обнаруживать ошибки, возникающие при передаче данных по шине PCI.

Возможные варианты значений:
Disable — генерирование PERR# отключено
Enable — генерирование PERR# включено

Perr generation что это в биосе

Core version number for a specific release. Format is XX.YY, where:

XX — Core major release.

YY — Core minor release.

Compliancy version number for a specific release. Format is UEFI version number and Platform Initialization (PI) version number.

Example: UEFI 2.8; PI 1.7

BIOS project version number for a specific release.

Example: 8400 17.00 x64

Build Date and Time

The date and time the build for the BIOS version was created.

BIOS release version. Format is XXYYZZPP, which indicates:

XX — Unique project/platform code.

YY — BIOS major release.

ZZ — BIOS minor release.

PP — Build number.

Total amount of memory in megabytes.

Example: 65536 MB

Allows you to change the current system date.

Example: Tue 11/08/2022

Allows you to change the current system time.

Advanced Menu

This section includes screens of the Advanced menu in the BIOS Setup Utility for Exadata Server X10M .

Force APCB Update

Force APCB Update

Trusted Computing 2.0 Options

The Trusted Computing 2.0 options are available only when you enable the Security TPM Device Support option.

TPM 2.0 Device Found

Displays the firmware version and vendor for the TPM (Trusted Platform Module) device.

Security TPM Device Support

Enable (default) or disable Trusted Platform Module (TPM) support. If disabled, the OS will not show TPM. Reset of the platform is required.

Active PCR banks

Displays active Platform Configuration Register (PCR) banks.

Available PCR banks

Displays available Platform PCR banks.

Displays if the SHA256 PCR bank is enabled (default) or disabled.

Schedule an operation for the security device.

Note: Your computer reboots during restart to change the state of a security device.

None (default), TPM Clear

Enable (default) or disable platform hierarchy.

Enable (default) or disable storage hierarchy.

Enable (default) or disable endorsement hierarchy.

PSP Firmware Versions

Displays the AMD Boot Loader (ABL) version number.

PSP Bootloader Version

Displays the Platform Security Processor (PSP) bootloader version.

Displays the AMD System Management Unit firmware version (SMU FW). The SMU is a microcontroller in the AMD EPYC processor that handles real-time events such as power management.

Displays the AMD Secure Encrypted Virtualization firmware version (SEV FW).

Displays the physical layer firmware (PHY FW) version.

MPIO FW Version

Displays the mass production I/O firmware (MPIO FW) version.

MMPDMA FW Version

Displays the Microprocessor Direct Memory Access (MMPDMA) firmware (FW) version.

Page Migration FW

Displays the Page Migration firmware (FW) version.

Displays the Global Memory Interconnect (GMI) firmware (FW) version.

uCode B0 Version

Displays the CPU stepping version, for example, B0.

Displays the AMD ASP Configuration Block (APCB) version.

Displays the AMD Generic Encapsulated Software Architecture (AGESA) PSP Outbput Buffer (APOB) version.

Displays the AGESA PSP PMU Block (APPB) version.

AMD CBS

AMD CBS Revision Number

Displays the AMD CBS revision number.

CPU Common Options

With Force APCB Update enabled, allows you to customize overclock mode with Normal Operation or Customized settings.

With Force APCB Update enabled, allows you to select the number of active charge couple devices (CCDs). After you use this option to remove any CCDs, run a power cycle so that the settings you select in the future take effect. Default is Auto.

With Force APCB Update enabled, allows you to select the number of cores you want to use. After you use this option to remove any cores, run a power cycle so that the settings you select in the future take effect. Default is Auto.

With Force APCB Update enabled, you can disable symmetric multithreading (SMT). To re-enable SMT, select Enable and run a power cycle. Select Auto, based on the BIOS PCD (PcdAmdSmtMode) default setting. S3 is not supported on systems where SMT is disabled.

L1 Stream HW Prefetcher

With Force APCB Update enabled, allows you to enable (default) or disable the L1 Stream HW Prefetcher. Default is Auto.

L2 Stream HW Prefetcher

With Force APCB Update enabled, allows you to enable (default) or disable the L2 Stream HW Prefetcher. Default is Auto.

Platform First Error Handling

With Force APCB Update enabled, allows you to enable (default) or disable platform first error handling, cloak invidual banks, and mask deferred error interrupts from each bank.

Core Performance Boost

With Force APCB Update enabled, allows you to disable core performance boost. Default is Auto.

Global C-State Control

With Force APCB Update enabled, allows you to enable or disable the IO based C-state generation and DF c-states. Default is Auto.

SEV-ES ASID Space Limit

With Force APCB Update enabled, allows you to set space limits for Secure Encrypted Virtualization-Encrypted State address space identifier (SEV-ES ASID). SEV-ES and AMD Secure Nested Paging (SNP) guests must use ASIDs in the range 1 through 1086. For all ASIDs to support SEV-ES or SNP guests, set the value to 1007. The default is 1 which sets the space limits for all SEV guests and no SEV-ES or SNP guests.

With Force APCB Update enabled, allows you to enable (default) or disable SEV. To re-enable SEV, after you select Enable, run a power cycle.

SNP Memory (RMP Table) Coverage

With Force APCB Update enabled, allows you to enable, disable, or customize the entire system memory. Default is Auto.

With Force APCB Update enabled, allows you to enable or disable secure memory encryption enable (SMEE). Enabling both SMEE and Multi-Key Secure Memory Encryption (SME-MK) is not supported. Default is Auto.

Enhanced REP MOVSB/STOSB (ESRM)

With Force APCB Update enabled, allows you to enable (default) or disable memory security for Enterprise Security Management (ESRM). Default is 1. You can set the option to zero for analysis purposes, providing that the OS supports the option.

DF Common Options

NUMA Nodes Per Socket

With Force APCB Update enabled, allows you to specify the number of non-uniform memory access (NUMA) nodes per socket. Default is Auto. NPS1 specified one NUMA node per socket. NPS0 specified one NUMA node per system and attempts to interleave the two sockets together.

With Force APCB Update enabled, allows you to disable or enable memory interleaving. NUMA nodes per socket are recognized regardless of this setting. Default is Auto.

With Force APCB Update enabled, allows you to reamap DRAM out of the space below the 1TB bounday. Remapping depends on the DRAM configuration, NUMA node per socket (NPS), and interleaving selection, and might not always be possible. Default is Auto.

DRAM Map Intervention

With Force APCB Update enabled, allows you to invert the map so that the highest memory channels are assigned to the lowest addresses in the system. Default is Auto.

Location of Private Memory Regions

With Force APCB Update enabled, allows you to control whether the private memory regions (PSP, SMU and CC6) are at the top of DRAM, at the top of the 1st DRAM pair, or distributed. The Distributed option requires memory on all dies. The location of the private memory regions is always at the top of DRAM if some dies do not have memory, regardless of the setting. The Consolidate option for the first DRAM pair is only valid for non-interleaved memory. Default is Auto.

With Force APCB Update enabled, allows you to specify the maximum frequency for the inter-chip global memory interconnect (XGMI) PState in a 4-link or 3-link topology. Default is Auto.

UMC Common Options

DDR Controller Configuration

DDR Power Options

Sub Urgent Refresh Lower Bound

With Force APCB Update enabled, allows you to specify the stored refresh limit required to enter sub-urgent refresh mode. The minimum limit is 1 and the maximum limit is 6. Default is 1.

Urgent Refresh Limit

With Force APCB Update enabled, allows you to specify the stored refresh limit required to enter urgent refresh mode. The minimum limit is 1 and the maximum limit is 6. Default is 4.

DRAM Refresh Rate

With Force APCB Update enabled, allows you to specify the DRAM refresh rate to 3.9 usec (default) or 1.95 usec.

Self-Refresh Exit Staggering

With Force APCB Update enabled, allows you to specify the amount to stagger the self-refresh exit. Tcksrx += (Trfc/n * (UMC_Number % 3)) To disable staggering, select n=1. Default is n=9.

Double Data Rate Self-Testing Memory Built-in Self Test (DDR MBIST) Options

DDR Healing BIST Options

With Force APCB Update enabled, allows you to enable or disable (default) running a full memory content test and is separate and distinct from the MBIST test of Interface and Data Eye. The PMU Mem BIST option uses PMU firmware to test the memory on all channels simultaneously. Failing memory is repaired using soft or hard PPR, depending on the PPR configuration. The Self-Healing Mem BIST option runs the JEDEC DRAM self healing test, if the device and DIMM support the self-healing. The DRAM does a hard repair for any failing memory. The Power Management Unit (PMU) and Self-Healing Mem BIST option runs the PMU Mem BIST and then the Self-Healing Mem BIST tests sequentially.

With Force APCB Update enabled, enables a memory content test.

PMU Mem BIST Algorithm

With Force APCB Update enabled, allows you to select PMU Mem BIST algorithms.

DDR Healing BIST Repair Type

With Force APCB Update enabled, for DRAM errors found in the BIOS memory BIST, select the repair type: Soft, Hard, or Test only. Do not attempt to repair.

Double Data Rate Row Address Strobe (DDR RAS)

With Force APCB Update enabled, allows you to specify the Unified Management Console (UMC) error injection configuration where writes are disabled. Default is Auto.

With Force APCB Update enabled, allows you to enable or disable transparent SME. Default is Auto.

With Force APCB Update enabled, allows you to enable or disable (default) SME-MK encryption mode. Enabling both SMEE and SME-MK is not supported.

Non-blocking Input Output (NBIO) Options

With Force APCB Update enabled, allows you to enable or disable I/O Memory Management Unit (IOMMU). Default is Auto.

With Force APCB Update enabled, allows you to enable or disable Access Control Services (ACS). You must enable Advanced Error Reporting (AER) for ACS to work. Default is Auto.

PCIe ARI Support

With Force APCB Update enabled, allows you to enable (default) or disable Alternative Routing-ID Interpretation (ARI).

System Management Unit (SMU) Common Options

Thermal Design Power (TDP) Control

With Force APCB Update enabled, allows you to use the fused Thermal Design Power TDP (Auto) or set customized TDP (Manual). Default is Manual.

With Force APCB Update enabled, allows you to set TDP in decimal format. The minimum value is 0 and the maximum value is 4294967295. Default is 400.

Package Power Tracking (PPT) Control

With Force APCB Update enabled, allows you to use the fused PPT (Auto) or set customized PPT (Manual. Default is Manual.

With Force APCB Update enabled, allows you to set PPT in decimal format. The minimum value is 0 and the maximum value is 4294967295. Default is 400.

With Force APCB Update enabled, allows you to use the default performance determinism settings (Auto) or set custom performance determinism settings (Manual). Default is Manual.

With Force APCB Update enabled, allows you to specify Power (default) or Performance for determinism control.

xGMI Link Width Control

With Force APCB Update enabled, allows you to use the default xGMI link width controller settings (Auto) or set custom xGMI link width controller settings (Manual). Default is Manual.

xGMI Force Link Width Control

With Force APCB Update enabled, you can specify not forcing the xGMI to a fixed width (Unforce) or force the xGMI link to a specified width. Default is Force.

xGMI Force Link Width

With Force APCB Update enabled, you can set the xGMI force link width at 2 (x16), 1 (x8), or 0 (x4). Default is 2.

xGMI Max Link Width Control

With Force APCB Update enabled, you can use the default xGMI maximum supported link width (Auto) or set a custom xGMI maximum link width (Manual). Default is Manual.

xGMI Max Link Width

With Force APCB Update enabled, you can select 0 to set the maximum xGMI link width to x8 or select 1 (default) to set the maximum xGMI link width to x16.

Algorithm Performance Boost Disable (APBDIS)

With Force APCB Update enabled, you can select 0 to set mission mode and not use APBDIS or select 1 (default) to use APBDIS.

With Force APCB Update enabled, when you use APBDIS, you can set the Data Fabric P-State (DfPstate) index from 0-4. Default is 0.

NBIO RAS Common Options

PCI AER Reporting Mechanism

With Force APCB Update enabled, allows you to select the method of reporting AER errors from PCI Express. Firmware First allows BIOS to handle errors first through the generation of a system management interrupt (SMI). Otherwise OS First (default) allows the OS to handle the errors first through the generation of a system control interrupt (SCI).

With Force APCB Update enabled, enable or disable Advanced Error Reporting capability. Default is Auto.

With Force APCB Update enabled, enable or disable (default) support for Secure Encrypted Virtualization and Secure Nested Paging.

SoC Miscellaneous Control

ABL Console Out Control

With Force APCB Update enabled, enable or disable the ConsoleOut Function for ABL. Default is Auto.

ABL Basic Console Out Control

With Force APCB Update enabled, enable or disable the Basic ConsoleOut Function for ABL. Default is Auto.

ABL PMU Message Control

With Force APCB Update enabled, enable or disable PMU message for ABL. Default is Auto.

Serial Port Console Redirection

COM0 Console Redirection Settings

Console Redirection EMS

Enable or disable (default) console redirection EMS.

Enable (default) or disable console redirection.

VT100, VT100Plus (default), VT-UFT8, ANSI

Bits Per Second

9600, 19200, 38400, 57600, 115200 (default)

None (default), Even, Odd, Mark, Space

None (default), Hardware, Request to Send or Clear to Send (RTS/CTS)

PCI Subsystem Settings

PCI Driver Version

Version number of the PCI driver.

PCI Settings Common for All Devices

Caution: If you change the PCI settings common to all devices, there might be unwanted results, such as the system might freeze.

PCI Latency Timer

Specify a PCI Bus Clock value (32 (default) 64, 96, 128, 160, 192, 224, 248) to use for the PCI Latency Timer Register.

PCI-X Latency Timer

Specify a PCI Bus Clock value (32, 64 (default), 96, 128, 160, 192, 224, 248) to use for the PCI-X Latency Timer Register.

VGA Palette Snoop

Enable or disable (default) the PCI cards to snoop on the video card palettes and register snooping.

Enable or disable (default) the PCI device to generate PERR#.

Enable or disable (default) the PCI device to generate SERR#.

Above 4G Decoding

Enable (default) above 4G decoding only if the system supports 64 bit PCI decoding or disable the option.

Enable (default) or disable Single Root I/O Virtualization (SR-IOV) to configure devices into multiple virtual devices that can be used on virtual OS installations. If supported by the hardware and set to enabled, all devices on the system that are SR-IOV capable are configured to support SR-IOV and I/O resources are allocated to the device as normal. If set to disabled, I/O resources are not allocated to the device.

BME DMA Mitigation

Enable or disable (default) Bus Master Attribute (BME) Direct Memory Access (DMA) that is disabled after PCI enumeration for PCI bridges, after SMM is locked.

PCI Express Settings

PCI Express Device Register Settings

Enable (default) or disable PCI Express device relaxed ordering.

Enable to allow device to use the 8-bit tag field as a requester or disable (default) the option.

Enable (default) the PCI Express device no snoop option or disable the option.

Select the maxium payload for a PCI Express device or select Auto (default) to allow BIOS to select the value.

Maximum Read Request

Select the maxium read request size for a PCI Express device or select Auto (default) to allow BIOS to select the value.

PCI Express Link Register Settings

By default, the Active State Power Management (ASPM) option is disabled. Select Auto to allows BIOS to configure ASPM. Select Force L0s to force all links to the L0s state. Warning : Enabling ASPM might cause some PCIe devices to fail.

Link Training Retry

Specifies the number of retry attempts (2, 3, or 5) that the software makes to retrain the link, if a previous attempt was unsuccessful. Default is 5.

Link Training Retry Timeout

Specifies the number of microseconds the software waits before polling the Link Training bit in the Link Status register. The valus are 10-10000 uS. Default is 1000.

To save power, the software disables the unpopulated PCIe links if you select Disable Link. Default is Keep Link ON.

In device functions that support completion timeout, allows the system software to change the Completion Timeout value. Default is 50 us to 50 ms. You can select Shorter or Longer to change the timeout length of time or disable the timeout.

If Alternative Routing ID Interpretation (ARI) Forwarding is supported by the hardware and enabled, the Downstream Port disables its Device Number field of 0 enforcement, when turning a Type1 Configuration Request into a Type0 Configuration Request. Enabling ARI Forwarding allows access to Extended Functions in an ARI Device immediately below the port. Default is Disabled.

AtomicOp Requester Enable

If supported by hardware and enabled, Atomic Operation (AtomicOp) Requester initiates AtomicOp Requests only if the Bus Master Enable bit is in the Command Register Set. Default is Disabled.

AtomicOp Egress Blocking

If supported by hardware and enabled, outbound AtomicOp Requests through the Egress Ports are blocked. Default is Disabled.

IDO Request Enable

If supported by hardware and enabled, allows you to set the number of ID-Based Ordering (IDO) bit (Attribute[2]) requests to be initiated. Default is Disabled.

IDO Completion Enable

If supported by hardware and enabled, allows you to enable ID-Based Ordering (IDO) Completion bit. Default is Disabled.

LTR Mechanism Enable

If supported by hardware and enabled, allows you to enable the Latency Tolerance Reporting (LTR) Mechanism. Default is Disabled.

End-End TLP Prefix Blocking

If supported by hardware and enabled, allows you to block forwarding of Traffic Light Protocols (TLPs) that contain End-End TLP Prefixes. Default is Disabled.

PCI Express GEN2 Link Register Settings

Target Link Speed

If supported by hardware and you select Force to X.X (2.5, 5.0, 9.0, 16.0, or 32.0) GT/s for downstream ports, you set an upper limit on the link operational speed by restricting the values advertised by the upstream component in its training sequences. Auto (default) uses hardware initialized data.

Clock Power Management

If supported by hardware and and enabled, the device uses the CLKREQ# signal for power management of the link clock, with the protocol defined in the form factor specification. Default is Disabled.

If supported by hardware and and enabled, forces Link Training and Status State Machine (LTSSM) to send Sealed Key Protection (SKP) Ordered Sets between sequences when sending Compliance Pattern or Modified Compliance Pattern. Default is Disabled.

Hardware Autonomous Width

If supported by hardware and and disabled, the hardware cannot change the link width except for width size reduction to correct an unstable link operation. Default is Enabled.

Hardware Autonomous Speed

If supported by hardware and and disabled, the hardware cannot change the link speed except for speed rate reduction to correct an unstable link operation. Default is Enabled.

PCI Hot-Plug Settings

BIOS Hot-Plug Support

Allows BIOS build in Hot-Plug support, if the operating system does not support PCI Express and Standard Hot-Plug Controller (SHPC) hot-plug natively. Default is Enabled.

PCI Buses Padding

Pads the PCI buses behind the bridge for hot-plug. Select 1-5. Default is 1.

I/O Resources Padding

Pads the I/O resources behind the bridge for hot-plug. Select 4 K, 8 K, 16 K, or 32 K. Default is 4K.

MMIO 32 Bit Resources Padding

Pads the PCI Memory-Mapped IO (MMIO) 32-bit resources behind the bridge for hot-plug. Default is 16 M.

PFMMIO 32 Bit Resources Padding

Pads the PFMMIO 32-bit prefetchable resources behind the bridge for hot-plug. Default is 16 M.

PFMMIO 64 Bit Resources Padding

Pads the PFMMIO 64-bit prefetchable resources behind the bridge for hot-plug. Default is disabled.

NVMe Configuration

Displays the model number, size, vendor ID, device ID, and namespace for the NVMe controller.

NVMe Device Self Test

Allows you to change the type of self test, Short (default) or Extended, change the self test action, Controller Only Test (default) or Controller and Namespace, and run a self test based on the option and action you selected.

Network Stack Configuration

Enables (default) the UEFI network stack and prevents users from performing single-user network boots and network installations. If disabled, the host does not use the network interface.

IPv4 PXE Support

Enables (default) IPv4 PXE Boot support. If disabled, the IPv4 PXE Boot Option is not supported.

IPv4 HTTP Support

Enables IPv4 HTTP Boot support. If disabled (default), the IPv4 HTTP Boot Option is not supported.

IPv6 PXE Support

Enables IPv6 PXE Boot support. If disabled (default), the IPv6 PXE Boot Option is not supported.

IPv6 HTTP Support

Enables IPv6 HTTP Boot support. If disabled (default), the IPv6 HTTP Boot Option is not supported.

PXE Boot Wait Time

Specifies the wait time to press the ESC key to abort the PXE boot. Default is 0.

Media Detect Count

Specifies the number of times the presence of physical storage devices are verified on a system reset or power cycle. Default is 1.

SATA Configuration

Displays the SATA controller BUS device and function, and installed media devices.

CPU Configuration

Enable (default) or disable CPU virtualization.

Displays the information for each node in the CPU.

Displays the CPU ID.

Displays the number of cores.

Displays the number of threads.

Displays the processor family for the CPU.

Displays the processor model for the CPU.

Microcode Patch Level

Displays the microcode patch level.

Displays the amount of cache per core for the L1 Instruction Cache, L1 Data Cache, L2 Cache, and L3 Cache Per Socket.

Disk Freeze Lock Settings

Disk Freeze Lock Settings

Disk Freeze Lock

Enables or disables (default) disk freeze lock, which prevents disks from being sanitized. Disk types include NVMe and M.2.

USB Ports

External USB Port

Enables or disables (default) the external USB port.

IO Menu

This section includes screens of the IO menu in the BIOS Setup Utility for Exadata Server X10M .

Internal Devices

Displays and provides options to change the internal device settings.

PCI-E UEFI Driver Enable

Enable (default) or disable PCI-E UEFI Driver. If set to enabled, UEFI Driver for the card executes as normal. If set to disabled, UEFI Driver for the card is not copied into memory and the execution of the UEFI Driver is inhibited.

Add-in Cards

Displays and provides options to change the settings of the devices in PCIe slots.

PCIe UEFI Driver Enable

Enable (default) or disable PCI-E UEFI Driver. If set to enabled, UEFI Driver for the card executes as normal. If set to disabled, UEFI Driver for the card is not copied into memory and the execution of the UEFI Driver is inhibited.

Displays and provides options to change the settings of the devices in NVMe slots.

PCIe Connector Special Configuration

Slot 1-9 PCIe Connector Configuration

Specify the connector to control PCIe bifurcation and hotplug.

Security Menu

Secure Boot is activated when Platform Key (PK) is enrolled, System mode is User (default) or Deployed, and the Compatibility Support Module (CSM) function is disabled.

Attempt Secure Boot

When enabled (default), Secure Boot is activated when Platform Key (PK) is enrolled, System mode is User or Deployed, and the Compatibility Support Module (CSM) function is disabled.

Secure Boot Mode

Specifies Standard or Custom (default) Secure Boot mode. In Custom mode, you can configure secure boot policy variables by a physically present user without full authentication.

Restore Factory Keys

Forces system to User mode. Installs factory default Secure Boot key databases.

Reset to Setup Mode

Removes all secure boot key databases from NVRAM.

Enter Audit Mode

Resets the system to Audit Mode workflow and erases the PK variable.

Enter Deployed Mode

Transitions between Deployment and User modes.

Allows expert users to change Secure Boot Policy variables without variable authentication.

Factory Key Provision

Enables (default) provisioning factory default Secure Boot keys after the platform reset and while the system is in Setup Mode.

Restore Factory Keys

Forces the system to User mode. Installs factory default Secure Boot key databases.

Enrolls an EFI image to run in Secure Boot mode. Enroll SHA256 Hash certificate of a PE image into Authorized Signature Database.

Export Secure Boot Variables

Select a file system to copy the NVRAM content of Secure Boot variables to files in a root folder on a file system device.

Secure Boot Variable | Size | Keys | Key Source

Displays the size, platform keys, key exchange keys, and signatures.

Boot Menu

Disable (default) or enable to add the EFI Shell to the Boot Priority List.

Retry Boot List

Disable or enable (default) automatic retries of the Boot List when all devices fail.

Network Boot Retry

If enabled (default), BIOS automatically retries the PXE list present in the system when all PXE attempts have failed. If set to disabled, the system halts and displays the error message “Network Boot Failed” when all PXE boots fail. If set to Boot List, fails over to the main Boot Options Priority list.

Persistent Boot Support

Disable (default) reverts to the default boot handing for the next boot.

Boot Option Priorities

Displays and sets the system boot order.

Exit Menu

Save Changes and Exit

Save changes and exit the BIOS Setup Utility.

Discard Changes and Exit

Exit the BIOS Setup Utility without saving changes.

Discard any changes made to the setup options.

Restore and load the optimal default values for all of the setup options.

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